Business Wire

ProDesign Joins Synopsys in-Sync Program to Enable Unified ASIC Prototyping and Verification; Common ASIC Flow Optimized for Customer Productivity

SAN JOSE, Calif.--(BUSINESS WIRE)--April 4, 2005--ProDesign USA, a leading supplier of high-speed FPGA-based ASIC verification platforms, today announced that it has joined the Synopsys in-Sync(R) ...
Outlookindia

Bridging The Talent Gap In ASIC Design, Verification, And Silicon Validation

As technology continues to evolve, the need for semiconductor chips also increases. The semiconductor industry lies underneath much of the technological progress, powering devices and systems that ...
EDN

SOC ASICs: overcoming verification and validation challenges

With any semiconductor device, presilicon design verification and postsilicon validation are critical to the functional and operational quality of the finished product. This situation holds especially ...
Design-Reuse

Test engineers must join ASIC flow early

Paul Taubman is a senior design engineer for Tality Corp., Cadence Design Systems' services organization. In this article he shows how test engineers should interact with designers in order to ...
Electronic Design

FPGA Prototyping Tool Aligns With ASIC Flow

This FPGA-Synthesis Tool Offers The Prototyping Capabilities Required By RF-Intensive Systems And A Migration Path To ASIC Product Design. Over a third of all high-end ASIC designers now use FPGAs for ...
EDN

Focus is on the best ASIC design flow

System-on-programmable-chip technology has characteristics of both board-based design and ASIC-based system-on-a-chip ASIC design. The immediate attraction of SoPC is that, like a breadboard, the ...
Design-Reuse

Magma and ChipX Extend Integrated RTL-to-GDSII Design Flow to Next-Generation Structured ASIC Designs

Magma Blast Create SA, Blast Fusion SA and ChipX CX6000 Structured ASIC combine to reduce cost and cycle time of high-performance designs SANTA CLARA, Calif., Nov. 9, 2005 - ChipX, the structured ASIC ...